1.1 State of the Art
1.2 Problems
With the units of today (FPGAS, DPGAs, etc.), synchronization of the configurable elements is usually based on the clock pulse of the unit. This type of time-controlled synchronization poses many problems, because it is often not known in advance how much time a task will require until a final result is available. Another problem with time-controlled synchronization is that the event upon which the synchronization occurs is not triggered by the element to be synchronized itself but instead by an independent element. In this case, two different elements are involved in the synchronization. This leads to much higher management overhead.
1.3 Improvement Through the Invention
This invention describes a method which makes it possible for the synchronization to be based on the elements to be synchronized themselves. Synchronization is no longer implemented or administered by a central instance. By making synchronization the responsibility of each element, many more synchronization tasks can be carried out at the same time, because independent elements no longer interfere with each other in accessing the central synchronization instance. The patent claims concern details and specific embodiments as well as features of the synchronization method according to this invention.
2. Description of the Invention
2.1 Overview of the Invention; Abstract
In a unit with a two- or multi-dimensional, programmable cell architecture (DFP, DPGA), any configurable element can have access to the configuration and status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. Thus, in addition to the usual method, the configuration may also take place from the processing array (PA, see PACT02) through a primary logic unit.
2.2 Detailed Description of the Invention
The invention starts with a run-time programmable, run-time reconfigurable unit. The configurable elements on the chip have one or more configuration registers for different tasks. Read and write access to these configuration registers is possible. In the method described here, it is assumed that for the following information, a configuration can be set in an element to be configured.                Interconnection register. The type of connection with other cells is set in this register.        Command register. The function to be carried out by the configurable element is entered in this register.        Status register. The cell stores its current status in this register. This status provides information to the other elements of the component regarding which processing cycle the cell is in.        
A cell is configured by a command which determines the function of the cell that is to be carried out. In addition, configuration data are entered to set the interconnection with other cells and the contents of the status register. The cell is ready for operation after this procedure.
To permit a flexible and dynamic interaction of multiple cells, each cell can have read or write access to all the configuration registers of another cell. The type of command with which the cell has been configured specifies to which of the many configuration registers will allow read or write access. Each command that can be executed by the cell exists in as many different modes of address as there are different independent configuration registers in an element to be configured.
Example: One cell has the configuration registers indicated above (interconnection, command and status) and is to execute the command ADD which performs addition. Through the various types of ADD command, it is now possible to select where the result of this function is to be transferred.                ADD-A. The result is transmitted to operand register A of the target cell.        ADD-B. The result is transmitted to operand register B of the target cell.        ADD-V. The result is transmitted to the interconnect register of the target cell.        ADD-S. The result is transmitted to the status register of the target cell.        ADD-C. The result is transmitted to the command register of the target cell.        
In addition to the result, each cell can generate a number of trigger signals. The trigger signals need not necessarily be transmitted to the same target cell as the result of processing the configured command. One trigger signal or a combination of multiple trigger signals triggers a certain action in the target cell or puts the cell in a certain status. A description of the states can be found in the following text. There are the following trigger signals:                GO trigger. The GO trigger puts the target cell in the READY status.        RECONFIG trigger. The RECONFIG trigger sets the target cell in the RECONFIG status, so that the cell can be reprogrammed. This trigger is very appropriate especially in conjunction with switching tables. If it is assumed that the data to be processed is loaded into the operand registers at the rising edge of the clock pulse, processed in the period of the H level, and written to the output register at the trailing edge, then reconfiguration of the cell is possible at the trailing edge. The new configuration data is written to the command register at the trailing edge. The period of the L level is sufficient to successfully conclude the reconfiguration.        STEP trigger. The STEP trigger triggers a single execution of the configured command by the target cell that is in the WAIT status.        STOP trigger. The STOP trigger stops the target cell by setting the cell in the STOP status.        
Due to the possibility of indicating in the processing cell in which register of the target cell the result is to be entered and which type of trigger signal is to be generated, a quantity of management data can be generated from a data stream. This management data is not a result of the actual task to be processed by the chip, but instead serves only the function of management, synchronization, optimization, etc. of the internal status.
Each cell can assume the following states, which are represented by appropriate coding in the status register:                READY. The cell has been configured with a valid command and can process data. Processing takes place with each clock cycle. The data is entered into the register of the target cell on the basis of the addressing type of the cell sending the data.        WAIT. The cell has been configured with a valid command and can process data. Processing takes place in part on the basis of a trigger signal which can be generated by other elements of the unit. The data is entered into the register of the target cell on the basis of the addressing type of the cell sending the data.        CONFIG. The cell has not been configured with a valid command. The data packet which is sent to the cell with the next clock cycle is entered into the command register. The data packet is in any case entered into the command register, regardless of which addressing type has been used by the cell sending the data.        CONFIG WAIT. The cell has not been configured with a valid command. A data packet is entered with the next trigger signal which can be generated by other elements of the unit and can be written to the command register. The data packet is entered into the command register in any case, regardless of which addressing type has been used by the cell sending the data.        RECONFIG. The cell has been configured with a valid command, but it is not processing any data at the moment. The data is accepted by the cell (transferred to the input register) but is not processed further.        STOP. The cell is configured with a valid command, processed, but no data so far. The data is received by the cell (transmitted to the input register) but not further processed.        
Due to these various states and the possibility of read and write access to the various registers of a cell, each cell can assume an active management role. In contrast with that, all existing units of this type have a central management instance which must always know and handle the overall status of the unit.
To achieve greater flexibility, there is another class of commands which change in type after the first execution. Using the example of the ADD command, the command has the following format:                ADD-C-A. The result of the ADD function is written to the command register of the target cell with the first execution of the command. With each subsequent execution, the result is written to operand register A.        
This possibility can be expanded as much as desired, so that commands of the type ADD-C-V-A-C- . . . B are also conceivable. Each command can assume all permutated combinations of the different addressing and triggering types.
2.3 Hardware Expansion with Respect to PACT02
2.3.1 Additional Registers
A status register and a configuration register are added to the registers described in PACT02. Both registers are triggered by the PLU bus and they have a connection to the state machine of the SM UNIT (PACT02, FIG. 2: 0213).
2.3.2 Change in the PLU Bus
In PACT02, the configurable registers M/F-PLUREG are managed exclusively over the PLU bus (PACT02, FIG. 2: 0210). To ensure the function according to this invention, there must also be an additional possibility of access through the normal system bus (PACT02, FIG. 2: 0201). The same thing is true of the new status and configuration registers.
Only the part of the system bus that is interconnected with the PAE over the BM UNIT (PACT02, FIG. 2: 0210) is relevant for the registers. Therefore, the bus is relayed from the BM UNIT to the registers, where upstream multiplexers or upstream gates assume the switching between the PLU bus and the system bus relevant for the PAE.
The multiplexers or gates are wired so that they always switch through the system bus relevant for the PAE except after a reset of the unit (RESET) or when the ReConfig signal (PACT02, FIG. 3: 0306) is active.
2.3.3 Expansion of the System Bus
The system bus (PACT02, FIG. 2: 0201) is expanded to the extent that the information about the target register is transmitted together with the data. This means that an address which selects the desired register at the data receiver is also sent at the same time.